Wikidata

(Q104152389)

English

SweRV

first open RISC-V processing core design and series of its descendants

In more languages

Statements

developer
Western Digital
0 references
software version identifier
1.2
publication date
22 January 2021
1 reference
reference URL
https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.2
retrieved
23 January 2021
title
Release 1.2 (English)
publication date
22 January 2021
1.5
publication date
22 January 2021
1 reference
reference URL
https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.5
retrieved
23 January 2021
title
Release 1.5 (English)
publication date
22 January 2021
1.6
publication date
22 January 2021
1 reference
reference URL
https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.6
retrieved
23 January 2021
title
Release 1.6 (English)
publication date
22 January 2021
1.7
publication date
22 January 2021
1 reference
reference URL
https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.7
retrieved
23 January 2021
title
Release 1.7 (English)
publication date
22 January 2021
1.8
publication date
22 January 2021
1 reference
reference URL
https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.8
retrieved
23 January 2021
title
Release 1.8 (English)
publication date
22 January 2021
1.9
publication date
3 February 2021
1 reference
reference URL
https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.9
retrieved
22 February 2021
title
Release 1.9 (English)
publication date
3 February 2021
 
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