Wikidata

Wikidata:Property proposal/Cache

< Wikidata:Property proposal

cache edit

Originally proposed at Wikidata:Property proposal/Generic

   Not done
Descriptionhardware component that stores data for computing
Representscache (Q165596)
Data typeItem
Domainproperty
Allowed valuesone or multiple items that hold integer numbers
Allowed unitsByte or exponential values (kilobyte, megabyte, etc.)
Example 1AMD Phenom II X6 1090T (Q66481199) → L1 cache (Q28972913): 8 x 64 KB (4-way set associative) + 8 x 32 KB (8-way set associative), L2 cache (Q12635161): 8 x 512 KB (16-way set associative exclusive caches), L3 cache (Q28972917): 6 MB (48-way set associative cachevalue, shared)[1]
Example 2AMD Ryzen Threadripper 1900X (Q56062710) → L1 cache (Q28972913): 6 x 64 KB (2-way set associative instruction caches) + 6 x 64 KB (2-way set associative data caches), L2 cache (Q12635161): 6 x 512 KB (16-way set associative exclusive caches), L3 cache (Q28972917): 2 x 8 MB (16-way set associative)[2]
Example 3Pentium N3700 → L1 cache (Q28972913): 4 x 32 KB (8-way set associative) + 4 x 24 KB (6-way set associative), L2 cache (Q12635161): 2 x 1 MB (16-way set associative)[3]
Sourceen:Cache (computing)
Planned useCan be used for every object that has some form of cache

Motivation edit

I'm working on AMD Phenom II X6 1090T (Q66481199) and want to include as much information has possible so that I can use it as template. The cache information is a very important part of a CPU.

There were already two property proposals that suggested the same, but ended in the middle of nowhere and were withdrawn afterall.

The structure would be like this (example below keep the parts that should be read together):

  • Cache: (property)
    • L1/2/3/4 cache (item)
      • L1/2/3/4 cache value
        • value information (applies to)

Information could also not only be added about the type and it's size, but also

  • cache latency
  • cache connection (how many lanes the caches uses to connect to the CPU/IO unit)
  • cache storage type (is the cache only responsible to hold a specific type of data like instructions or data)
  • cache exclusiveness (is the cache per CPU core, per CPU module (eg. AMD Bulldozer architecture) or is it shared for all)
  • cache area (how much area does the cache use. This could be interesting with AMDs chiplet design when maybe different types of cache sits on different chiplets in different manufacturing sizes)

Since there already were some comments on the last proposals I will try to answer them:

  • @GPSLeo:: Should we use multiple properties?: I don't care if there is one or more properties. I want to make it as flexible as possible so that the cache of rather exotic CPUs are much easiert to include when they are only items.
  • @Visite fortuitement prolongée:: We could use memory capacity (P2928) with qualifiers: Is all cache in every IT product volatile? The property seems more to be used in items where there is a fixed ammount of maximum RAM (eg. phones). This usecase is also the only listed case for as property example.
  • @TomT0m:: We could use has part(s) (P527): It would be the same layout, but I do not want to jam all the cache into something that could also house all other values in the item. Some items use has part(s) of the class (P2670) (Q56062710#P2670) and uses (P2283) (Q51963118#P2283). Since there seems to be no clear wy of how to include such an information there are already multiple forms of it.


Example for AMD Phenom II X6 1090T (Q66481199):

  • L1 cache:
    • 6 x 64 KB
      • applies to associative instruction cache
      • connection 2-way
      • dispersion one per core
    • 6 x 64 KB
      • applies to associative data cache
      • connection 2-way
      • dispersion one per core
  • L2 cache:
    • 6 x 512 KB
      • applies to associative exclusive cache
      • connection 16-way
      • dispersion one per core
  • L3 cache:
    • 6 MB
      • applies to associative cache
      • connection 48-way
      • dispersion shared

Discussion edit

Ping to all missing: @ديفيد عادل وهبة خليل 2:, @Dhx1:, @Amitie 10g:, @MisterSanderson:, @Tobias1984:, @Srittau:, @Jsamwrites:, @Tinker Bell:, @SixTwoEight:
  WikiProject Informatics has more than 50 participants and couldn't be pinged. Please post on the WikiProject's talk page instead.

If you have any idea or comment don't hesitate to post it! --D-Kuru (talk) 15:28, 2 December 2019 (UTC)[reply]

If you already found a workaround please show me the example above in a real item --D-Kuru (talk) 18:48, 2 December 2019 (UTC)[reply]
Processor cache? edit

I'm still new to Wikidata, so I'll reason in more general terms. First, the use case mentioned here looks extremely useful. However, if I look at "cache" usage in hardware, I've some issues with the way the use case mentioned above is implemented:

  • Hard disk have "cache", in some hard disks, the cache consists of RAM chips.
  • Hard disk, or other storage system (a LVM2 volume group for instance) can also have a very different type of "cache" which consist in using faster non-volatile storage like SSDs.

A way to deal with that would be to use the work "processor cache" instead:

  • I don't know any CPU with RAM or SSD as cache for instance.
  • The kind of caches you are describing mainly applies to processors:
    • Discrete CPU caches may exists but they would still be meant for CPUs.

Some caveats:

    • I don't have enough knowledge of GPU architecture to know if they have caches or how it work.
    • I don't know enough FPGAs to see how it could apply there, but I know that some low end FPGA models have some internal volatile memory (block RAM or BRAM) that is different from the main RAM on the FPGA. This BRAM is documented a bit in the FOMU workshop.
    • I don't have knowledge of how chips doing computations without processors work. There were some ASICs done for mining crypto-coins for instance, and they may have some cache too.

In any case, if there are corner cases, the "processor cache" could probably still be abused to also describe the same kind of caches that could also be in use for other cases where there are no processors. For instance if there are caches in ASICs doing computations without processors, people would probably find it natural to refer to such caches as processor caches, even if there are no processor. GNUtoo (talk) 04:28, 3 February 2020 (UTC)[reply]

@GNUtoo: I only did include CPUs even there are much more devices that have a cache. Even the proposal started out with CPUs in mind there is no reason why it should be limited to them. If youhave eg. a HDD with NAND flash (Q13405492) as cache you would be able to use cache here as well.
I assume that "Cache" would be created as Property number 666 "P666":
If you know what type of cache it is you could apply this property to every item. --D-Kuru (talk) 22:53, 7 February 2020 (UTC)[reply]
First I think that Processor is better than CPU, because CPU has the word "Central" in it.
Because of that you could think of it as the main processor of a given system, even if it's sometimes it is instead used as a synonym of processor. Because of that it also tend to be relative to a given system. Your smartphone has a CPU, but the modem of your smartphone also has a CPU.
Processor also invite people to think about other architectures like DSP where there can be a cache. It's also more clear when you think of DSP as specialized processor.
As for using the cache and processor cache as synonym, I'm unsure that it's the same thing. There is a Wikipedia article about CPU cache here: https://en.wikipedia.org/wiki/CPU_cache and I'm not sure if all that also apply to other type of cache, like the SSD in SSHD, or cache volumes in LVM2 arrays. There is also the fact that in an LVM volume, the cache is not necessarily a hardware feature, but maybe we don't necessarily need to describe that feature of LVM2 in Wikidata in great accuracy. Maybe someone that knows more about storage cache could comment on that. If not there is another way we could try which would be to list all the properties a cache could have in either cases and look if they make sense for both processors and the NAND in an SSHD.
GNUtoo (talk) 23:35, 7 February 2020 (UTC)[reply]
Thinking more about it, "cache" could be a feature, which could be implemented by SRAM, NAND or processor cache, what do you think of that? For instance in a given SOC, the SRAM is typically used during boot to load the bootloader in memory, and the this bootloader initialize the external ram. I think that in some case this sram is used as a cache, once the SOC is booted. Also in Coreboot the cache is configured to be used as RAM, in order to be able to run the RAM initialization code which is written in C (and so it needs a stack and because of that RAM, or a special compiler, but the later ended up not being maintainable). The big challenge here would be to make sure that people do not make confusion between both. One would be a feature of computer architecture, and the other would be a hardware component / hardware block. GNUtoo (talk) 23:42, 7 February 2020 (UTC)[reply]
This proposal is NOT about a property for CPU/processor cache! It is about cache in general where CPUs were used as example. The property would allow to enter every tipe of cache you like. This applies not only to hardware, but also software cache of any type. --D-Kuru (talk) 18:45, 15 February 2020 (UTC)[reply]
Do you have examples on how to differentiate the cache made with SRAM, RAM and NAND on an SSHD? GNUtoo (talk) 17:12, 28 May 2020 (UTC)[reply]
You just add a qualifier to the statement using of (P642). So it would eg. 64KB of L1 cache (Q28972913). If it is a specialised cache (eg. instruction or data cache) it can be added using another qualifier --D-Kuru (talk) 21:17, 28 May 2020 (UTC)[reply]
It's unclear to me how that "other qualifier" would work in practice. Do I need to use has part (Q24575087)? or uses (P2283)? or has characteristic (P1552) ? GNUtoo (talk) 05:58, 30 May 2020 (UTC)[reply]

If we use L1, L2 and L3 caches or a generic CPU cache with a level as property, having properties would work anyway for either cases. The bonus here is that the L1, L2, and L3 caches already mention that they are CPU caches so it avoid the issue we've been discussing above. GNUtoo (talk) 06:17, 30 May 2020 (UTC)[reply]

By looking at the property examples I don't think has part is the correct choice here. Since there is eg. screenwriter (P58) and not a property named has staff I think it's fair to assume that a single property which describes cache is usable. I don't see any use in having a dozen different properties that can be collected in one. Since there are different cache types that may show up and vanish as products come and go I also don't think that there should be a seperate property for each since once the product runs out of production the property is pretty much useless.
Knowing that there already were proposals for different cache levels and that the discussion here is pretty much dead, I wager that there will be no adequat solution for this in the future
--D-Kuru (talk) 10:08, 31 May 2020 (UTC)[reply]
has part(s) (P527) seem right to me as various ASICs CPUs are made of silicon and have regions of the silicon that are dedicated to different functions. Softcores CPU can also have an ALU, a cache etc. The has part(s) (P527) property gives that example: Solar System (Q544) has part(s) (P527) Earth (Q2). So you could consider what's inside a specific CPU as a part of this specific CPU.
However I think I finally understood the point proposition. Is the "cache" property meant to represent a cache type?
For instance an AMD Phenom II X6 1090T (Q66481199) has part(s) (P527) L3 cache (Q28972917), but the L3 cache (Q28972917) "cache type" is an "associative instruction cache", and also has other properties like "connection 2-way". In that case it makes sense to do that as it's better than the current status. The issue is still that we'd need to propose a lot properties like "cache connection", and hope that they are generic enough and that new properties (like dielectric dissipation, or rowhammer factor, or whatever new property) don't pop up at each cache generation. In that case I think it'd be better to rename "cache" as "cache type" to be more clear. GNUtoo (talk) 22:58, 4 June 2020 (UTC)[reply]


  WikiProject Informatics has more than 50 participants and couldn't be pinged. Please post on the WikiProject's talk page instead. GNUtoo (talk) 22:59, 4 June 2020 (UTC)[reply]

Rationale for the ping: General computer hardware GNUtoo (talk) 22:59, 4 June 2020 (UTC)[reply]

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